yanghao1
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New ContributorF-Tile Serial Lite IV simulate 仿真
Hi, My design includes a f-tile serial lite iv ip and a system pll ip for it. When I try to run simulation for the design. The system pll's output port lock is dash line, and no clk out from pll ip....
Hi,
Try with the example design first.
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User...
Thank you,
Kshitij Goel
