Errors building Clocked Video Output

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I added a Clocked Video output to a design and feed it with a scatter-gather DMA. There are two Avalon ST adapters in the path to make it work.

I'm getting a bunch of errors like this:

"Error: IP Generator Error: Unable to set generic "USE_EMBEDDED_SYNCS" on entity "alt_vip_itc"- the parameter cannot be found on the entity"

I'm attaching a screenshot of the Quartus errors below.

The design is based on the Cyclone III starter kit example from the nioswiki. It contains a CPU, SSRAM, SDRAM, flash and the SGDMA/CVO thing I added, no other video blocks.

Thanks,

Andrew

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Hi Andrew,

I suppose, the query in nios forum was posted by u about this issue. As i mentioned there, you will need to write a custom component, which will convert avalon streaming protocol(output of SGDMA) to avalon ST video prototcol(input of clocked video output).

without that, your design will not give correct functionality, even if you manage to compile it without error.

the avalon ST adapters are just for avalon streaming protocol and they will not solve the problem of avalon ST video protocol.

i suppose, these errors will be resolved once you put the custom component in your sopc builder.

good luck!

Also, forgot to mention, you will require to put a frame buffer before clocked video output IP for pixel rate throughput.

and the framebuffer IP also takes in the altera avalon ST video protocol.

Hi formjk,

Thanks for following up. The compile errors must be some weird artifact in one of my projects. I can successfully hook up an SGDMA to a Clocked Video Out with or without a framebuffer in between and build the whole thing in a separate new project.

I'm now studying the Avalon ST Video spec to figure out whether I really need a custom component or not. It seems that the signals are all there and it's a matter of sequencing and formatting the data correctly.

As to the framebuffer - I was hoping to just go straight from the SGDMA to the video out but you mention that it might not work due to throughput. Does the framebuffer have a faster way to master its way to the memory than the SGDMA? In that case, do I still need the SGDMA or can I just have the CPU fill the memory at the base address set up for the frame buffer?

Thanks,

Andrew

Hi Andrew,

it will be better not to write the gui directly into the framebuffer memory, as framebuffer memory will be read continuously at output pixel clock rate for clocked video output. and writing the GUI(using Nios) to the framebuffer memory may cause clash of memory read/write operations and there might be data corruption as NIos will not be able to write the GUI fast enough as it is required by the clocked video output IP. so it will b better to write GUI to other memory buffer using nios and using SGDMA to transfer this to framebuffer memory in streaming format.

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Hi Andrew,

I suppose, the query in nios forum was posted by u about this issue. As i mentioned there, you will need to write a custom component, which will convert avalon streaming protocol(output of sgdma) to avalon st video prototcol(input of clocked video output).

without that, your design will not give correct functionality, even if you manage to compile it without error.

the avalon ST adapters are just for avalon streaming protocol and they will not solve the problem of avalon ST video protocol.

i suppose, these errors will be resolved once you put the custom component in your sopc builder.

good luck!

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Does this custom component still needs to be made if using the latest version of QSys?

What QSys components are needed to be used to make the following dataflows:

1). Clocked Video Input -> SGDMA

2). SGDMA -> Clocked Video Output ?

I believe what you want to do is hook up a VIP frame reader to a clocked video output block.

See chapter 17, page 171 of this:

http://www.altera.com/literature/ug/ug_vip.pdf

Don't bother with the SGDMA.

The frame reader will allow you to render your frames using your microprocessor,

then "switch pages" once the backbuffer has completed rendering.

The framereader will then read out the completed frame over and over

until you switch to a new back buffer.

You won't need to write any custom HDL blocks to convert

from avalon streaming to VIP protocol if you use this block since

it will output VIP protocol automatically.

Hello, gwall!

If Your answer is to me, then in my case SGDMA is needed, because further SGDMA has to be hooked to PCIe Compiler ( PCIe Hard IP ):

1). Clocked Video Input -> SGDMA -> PCIe Compiler ( PCIe Hard IP )

2). PCIe Compiler ( PCIe Hard IP ) -> SGDMA -> Clocked Video Output

Aphraton,

In your case you will need to write a custom HDL block.

The reason for this is that the SGDMA does not know anything

about the VIP protocol.

Your pipeline might look something like:

Clocked Video Input -> VIP to streaming converter -> SGDMA -> PCIe Compiler ( PCIe Hard IP )

PCIe Compiler ( PCIe Hard IP ) -> SGDMA -> streaming to VIP converter ->Clocked Video Output

The streaming to VIP converter will need to generate VIP control packets

that describe the format of the video, and then pass through the

video data with appropriate start of packet and end of packet bits.

I think you also need to convert from ready latency 0 to ready latency 1 (for VIP).

The VIP to streaming converter will need to do the reverse of what I described above.

You may also want to use a frame buffer before your clocked video output

if for any reason the SGDMA block cannot output the data fast enough to

keep the clocked video output's internal FIFOs from starving.

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Aphraton,

In your case you will need to write a custom HDL block.

The reason for this is that the SGDMA does not know anything

about the VIP protocol.

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I thought, that SGDMA and Clocked Video Input / Output could be put together in QSys via QSys fabric without any "glue".

Are You sure, that this is not possible?

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You may also want to use a frame buffer before your clocked video output

if for any reason the SGDMA block cannot output the data fast enough to

keep the clocked video output's internal FIFOs from starving.

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Not only Clocked Video Output has FIFO.

SGDMA also seems to have built-in FIFO.

FPGA's internal memory also can be used as an additional FIFO to prevent Clocked Video Output's FIFO from underflowing.

What really can happen in Windows environement when all these FIFOs could be not enough and only presence of a Framebuffer could prevent loss of videodata?