Errors building Clocked Video Output

Aphraton,

In your case you will need to write a custom HDL block.

The reason for this is that the SGDMA does not know anything

about the VIP protocol.

Your pipeline might look something like:

Clocked Video Input -> VIP to streaming converter -> SGDMA -> PCIe Compiler ( PCIe Hard IP )

PCIe Compiler ( PCIe Hard IP ) -> SGDMA -> streaming to VIP converter ->Clocked Video Output

The streaming to VIP converter will need to generate VIP control packets

that describe the format of the video, and then pass through the

video data with appropriate start of packet and end of packet bits.

I think you also need to convert from ready latency 0 to ready latency 1 (for VIP).

The VIP to streaming converter will need to do the reverse of what I described above.

You may also want to use a frame buffer before your clocked video output

if for any reason the SGDMA block cannot output the data fast enough to

keep the clocked video output's internal FIFOs from starving.