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Altera_Forum
Honored Contributor
Honored ContributorErrors building Clocked Video Output
I added a Clocked Video output to a design and feed it with a scatter-gather DMA. There are two Avalon ST adapters in the path to make it work. I'm getting a bunch of errors like this: "...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Aphraton, In your case you will need to write a custom HDL block. The reason for this is that the SGDMA does not know anything about the VIP protocol. --- Quote End --- I thought, that SGDMA and Clocked Video Input / Output could be put together in QSys via QSys fabric without any "glue". Are You sure, that this is not possible?
