EMIF IPSupport

Questions: What target device is this? What are your parameter settings for the IP? What is the "ready" signal you are tapping? Is that supposed to be the Avalon waitrequest signal (which you should be tapping if you're not to know when the interconnect is ready to receive a read command). Remember, if waitrequest is low, you have to hold the read or write command on the bus until waitrequest goes low. You say this is the traffic generator so it should honor that, but it would be good to see in Signal Tap.

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The read burst transfer would expect to get the delay before the readdatavalid is coming after the waitrequest is triggered.

You may try to improve the controller efficiency by following the suggestion in the Agilex EMIF IP UG.

https://www.intel.com/content/www/us/en/docs/programmable/683216/23-2-2-7-1/improving-controller-efficiency.html

Regards,

Adzim

Thanks for your information we solved the issue.

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