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New Contributor

2 years ago

EMIF IPSupport

When simulating the EMIF IP with the example design, we encountered an issue where there was a random latency between the read_enable and read_valid signals. We couldn't identify the reason for this ...

TG Observations.pdf387 KB

Clarities needed in Traffic generator simulation Waveform.pdf2.1 MB

Memory

AdzimZM_Altera

Regular Contributor

2 years ago

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

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EMIF IPSupport

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