Forum Discussion
DillipriyaP
New Contributor
New ContributorEMIF IPSupport
When simulating the EMIF IP with the example design, we encountered an issue where there was a random latency between the read_enable and read_valid signals. We couldn't identify the reason for this ...
AdzimZM_Altera
Regular Contributor
Regular ContributorI’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
