Forum Discussion
DillipriyaP
New Contributor
1 year agoEMIF IPSupport
When simulating the EMIF IP with the example design, we encountered an issue where there was a random latency between the read_enable and read_valid signals. We couldn't identify the reason for this ...
sstrell
Super Contributor
1 year agoQuestions: What target device is this? What are your parameter settings for the IP? What is the "ready" signal you are tapping? Is that supposed to be the Avalon waitrequest signal (which you should be tapping if you're not to know when the interconnect is ready to receive a read command). Remember, if waitrequest is low, you have to hold the read or write command on the bus until waitrequest goes low. You say this is the traffic generator so it should honor that, but it would be good to see in Signal Tap.