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The read burst transfer would expect to get the delay before the readdatavalid is coming after the waitrequest is triggered.
You may try to improve the controller efficiency by following the suggestion in the Agilex EMIF IP UG.
https://www.intel.com/content/www/us/en/docs/programmable/683216/23-2-2-7-1/improving-controller-efficiency.html
Regards,
Adzim