DSP builder/Vhdl suggestion

Hi Tricky!

i have read in AN:427 that the format of YCbCr is

Y Cb Y Cr Y Cb Y Cr.

Further i want to enhance 4bit of Y to 8bit that.....

can you help me, please!

Thank you

Rizwan

thanks Tricky!

will you please guide me what type of digital processing is required ?

in other words what i have to do to enhance Y, such that i have 8bit Y data?

Best

Rizwan

Unless you add some filters to do some effects, you cant do allot to enhance Y because you've already thrown away half the data to make it only 4 bits. Appending zeros just puts it in the rage 0 to 255.

You could do some bilinear interpolation if you doubled the image size.

thanks Tricky!

i send you the file (ALT_ATLANTIC_SINK) that is having real time video in YCbCr format from the video daughter-card tvp5146, after this file i want only Y component.

please help me by code that i can put infront of ALT_ATLANTIC_SINK and having only Y component.

this Y component i want to input at VGA port to get Black & white image.

ALT_ATLANTIC_SINK is given by :

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

USE IEEE.numeric_std.ALL;

USE STD.textio.ALL;

USE work.ALT_CUSP_PACKAGE.ALL;

ENTITY ALT_ATLANTIC_SINK IS

GENERIC (

NAME : STRING := "";

SIMULATION : INTEGER := SIMULATION_OFF;

OPTIMIZED : INTEGER := OPTIMIZED_ON;

MANUFACTURER : INTEGER := MANUFACTURER_ALTERA;

FAMILY : INTEGER := FAMILY_STRATIX;

INIT_FILE : STRING := "UNUSED";

WIDTH : INTEGER := 16;

PAGE_SIZE : INTEGER := 1;

ADDRESS_WIDTH : INTEGER := 8; -- CEIL(LOG2(PAGE_SIZE))

MEM_WIDTH : INTEGER := 8; -- CEIL(LOG2(PAGES*PAGE_SIZE)

END_PACKET_USED: INTEGER := 0;

PAGES : INTEGER := 0; -- unused

LOG2_PAGES : INTEGER := 0; -- unused

WRITE_PORTS : INTEGER := 0; -- unused

FULL_AT_START : INTEGER := 0;

LATENCY : INTEGER := 1; -- must be 1

READY_LATENCY : INTEGER := 2

);

PORT (

clock : IN STD_LOGIC;

reset : IN STD_LOGIC;

----------------- CUSP SIDE SIGNALS

----------------------------------------------------------------------------

ena : IN STD_LOGIC := '1';

addr : IN STD_LOGIC_VECTOR( ADDRESS_WIDTH-1 DOWNTO 0) := (others=>'0');

rdata : OUT STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0);

takeb : IN STD_LOGIC := '0'; -- take a page - block if not there

takeb_en : IN STD_LOGIC := '0'; --

takenb : IN STD_LOGIC := '0'; -- take a page - do not worry

takenb_en : IN STD_LOGIC := '0'; --

wdata : IN STD_LOGIC_VECTOR( WIDTH-1 DOWNTO 0) := (others=>'0'); -- Unused

wdata_en : IN STD_LOGIC := '0';

page_to_take : OUT STD_LOGIC; -- a page is ready to take

returnnb : IN STD_LOGIC := '0'; -- give a page

returnnb_en : IN STD_LOGIC := '0'; --

eop : OUT STD_LOGIC;

stall : OUT STD_LOGIC;

----------------- ATLANTIC SIDE SIGNALS

----------------------------------------------------------------------------

-- atlantic signals

ready : OUT STD_LOGIC;

valid : IN STD_LOGIC := '1';

data : IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0) := (others=>'0');

startofpacket: IN STD_LOGIC := '0';

endofpacket : IN STD_LOGIC := '0'

);

END;

ARCHITECTURE rtl OF ALT_ATLANTIC_SINK IS

-- It takes 2 cycles for ready to react to valid, so we need buffering for

-- that as well as for READY_LATENCY (the time taken for valid to go low

-- after ready goes low)

CONSTANT DEPTH : INTEGER := READY_LATENCY + 2;

SIGNAL skid_full : STD_LOGIC_VECTOR(DEPTH-1 DOWNTO 0);

SIGNAL skid_data : STD_LOGIC_VECTOR((WIDTH * DEPTH)-1 DOWNTO 0);

SIGNAL skid_eop : STD_LOGIC_VECTOR(DEPTH-1 DOWNTO 0);

SIGNAL take : STD_LOGIC;

SIGNAL near_empty : STD_LOGIC;

SIGNAL empty : STD_LOGIC;

SIGNAL avail : STD_LOGIC;

SIGNAL skid_full2 : STD_LOGIC_VECTOR(DEPTH+1 DOWNTO 0);

SIGNAL skid_load : STD_LOGIC_VECTOR(DEPTH-1 DOWNTO 0);

BEGIN

-- The FU only ever drives takeb or takenb to get data out

take <= ((takeb AND takeb_en) OR (takenb AND takenb_en)) AND ena;

near_empty <= NOT skid_full(1);

empty <= NOT skid_full(0);

avail <= skid_full(0);

-- Stall the machine if there isn't any data

page_to_take <= avail;

stall <= (takeb AND takeb_en) AND NOT avail;

-- Latch the output data when requested. The cusp internals expect that

-- data will be maintained until it is replaced.

PROCESS(clock, reset)

BEGIN

IF reset = '1' THEN

rdata <= (others=>'0');

ELSIF clock'EVENT AND clock = '1' THEN

IF (avail AND take) = '1' THEN

rdata <= skid_data(WIDTH-1 DOWNTO 0);

END IF;

END IF;

END PROCESS;

-- Work out whether we're ready or not...

-- We're ready if there will be two spaces available on the next clock

PROCESS(clock, reset)

BEGIN

IF reset = '1' THEN

ready <= '0';

ELSIF clock'EVENT AND clock = '1' THEN

ready <= (take AND near_empty) OR empty;

END IF;

END PROCESS;

check_depth : IF DEPTH < 2 GENERATE

ASSERT FALSE REPORT "DEPTH must be at least 2" SEVERITY ERROR;

END GENERATE;

skid_full2 <= ( '0' & skid_full & '1' );

-- Copy the input data when it is presented

gen_skid : FOR I IN 0 TO DEPTH-1 GENERATE

skid_load(I) <= ( ((NOT take) AND (NOT skid_full(I)) AND skid_full2(I)) OR

(take AND skid_full(I) AND (NOT skid_full2(I+2))) );

PROCESS(clock, reset)

BEGIN

IF reset = '1' THEN

skid_full(I) <= '0';

skid_data(((I+1)*WIDTH-1) DOWNTO (I*WIDTH)) <= (others => '0');

ELSIF clock'EVENT AND clock = '1' THEN

IF (valid AND skid_load(I)) = '1' THEN

-- Load this entry of the FIFO

skid_full(I) <= '1';

skid_data(((I+1)*WIDTH-1) DOWNTO (I*WIDTH)) <= data;

ELSIF take = '1' AND I < DEPTH-1 THEN

-- If user has taken data then shift the FIFO

skid_full(I) <= skid_full(I+1);

skid_data((I+1)*WIDTH-1 DOWNTO I*WIDTH) <= skid_data((I+2)*WIDTH-1 DOWNTO (I+1)*WIDTH);

ELSIF take = '1' AND I = DEPTH-1 THEN

-- If user has taken data then shift the FIFO

skid_full(I) <= '0';

END IF;

END IF;

END PROCESS;

END GENERATE;

no_eop_generate: IF END_PACKET_USED = 0 GENERATE

eop <= '0';

END GENERATE;

eop_generate: IF END_PACKET_USED = 1 GENERATE

gen_eopskid : FOR I IN 0 TO DEPTH-1 GENERATE

PROCESS(clock, reset)

BEGIN

IF reset = '1' THEN

skid_eop(I) <= '0';

ELSIF clock'EVENT AND clock = '1' THEN

IF (valid AND skid_load(I)) = '1' THEN

skid_eop(I) <= endofpacket;

ELSIF take = '1' AND I < DEPTH-1 THEN

skid_eop(I) <= skid_data(I+1);

END IF;

END IF;

END PROCESS;

END GENERATE;

PROCESS(clock, reset)

BEGIN

IF reset = '1' THEN

eop <= '0';

ELSIF clock'EVENT AND clock = '1' THEN

IF (avail AND take) = '1' THEN

eop <= skid_eop(0);

END IF;

END IF;

END PROCESS;

END GENERATE;

END ;

Thank You

Rizwan