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Honored ContributorDSP Builder to ModelSim
Hi , im just perform RTL simulations with the ModelSim software. I add a TestBench block to my DSP builder model. Then I get the following error:
# ** Error: (vsim-3817) Formal port "clk" declared in the entity is not in the component. # Time: 0 ps Iteration: 0 Region: /tb_dpt2/dut File: ../DSPBuilder_dpt2_import/dpt2.vho # ** Error: (vsim-3817) Formal port "reset" declared in the entity is not in the component. # Time: 0 ps Iteration: 0 Region: /tb_dpt2/dut File: ../DSPBuilder_dpt2_import/dpt2.vho # ** Error: (vsim-3817) Formal port "data_in1" declared in the entity is not in the component. # Time: 0 ps Iteration: 0 Region: /tb_dpt2/dut File: ../DSPBuilder_dpt2_import/dpt2.vho # ** Error: (vsim-3817) Formal port "data_in2" declared in the entity is not in the component. # Time: 0 ps Iteration: 0 Region: /tb_dpt2/dut File: ../DSPBuilder_dpt2_import/dpt2.vho # ** Error: (vsim-3817) Formal port "data_in3" declared in the entity is not in the component. # Time: 0 ps Iteration: 0 Region: /tb_dpt2/dut File: ../DSPBuilder_dpt2_import/dpt2.vho # ** Error: (vsim-3817) Formal port "data_in4" declared in the entity is not in the component. # Time: 0 ps Iteration: 0 Region: /tb_dpt2/dut File: ../DSPBuilder_dpt2_import/dpt2.vho # ** Error: (vsim-3817) Formal port "data_in5" declared in the entity is not in the component. # Time: 0 ps Iteration: 0 Region: /tb_dpt2/dut File: ../DSPBuilder_dpt2_import/dpt2.vho # ** Error: (vsim-3817) Formal port "data_in6" declared in the entity is not in the component. # Time: 0 ps Iteration: 0 Region: /tb_dpt2/dut File: ../DSPBuilder_dpt2_import/dpt2.vho # ** Error: (vsim-3817) Formal port "data_in7" declared in the entity is not in the component. # Time: 0 ps Iteration: 0 Region: /tb_dpt2/dut File: ../DSPBuilder_dpt2_import/dpt2.vho # ** Error: (vsim-3817) Formal port "data_in8" declared in the entity is not in the component. # Time: 0 ps Iteration: 0 Region: /tb_dpt2/dut File: ../DSPBuilder_dpt2_import/dpt2.vho # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'input3' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'output4' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'input7' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'aclr' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'input8' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'clock' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'input4' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'output5' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'output1' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'output6' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'input5' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'input' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'output' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'dpt2_subsystem_output8' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'input2' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'output2' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'input6' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'output7' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'input1' is not on the entity.) # Region: /tb_dpt2/dut # ** Error: (vsim-3732) ./hdl/tb_dpt2.vhd(287): No default binding for component at 'dut'. # (Port 'output3' is not on the entity.) # Region: /tb_dpt2/dut # ** Fatal: Bad library format, library not compiled with ALTERA compiler. # # Time: 0 ps Iteration: 0 Instance: /tb_dpt2/clock File: UNKNOWN Line: 293 # FATAL ERROR while loading design # Error loading design # Unrecognized dataset prefix: sim can someone help me with this? thanks !!!
