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Altera_Forum's avatar
Altera_Forum
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17 years ago

DSP Builder to ModelSim

Hi , im just perform RTL simulations with the ModelSim software. I add a TestBench block to my DSP builder model. Then I get the following error: # ** Error: (vsim-3817) Formal port "clk" decl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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Is the name of your original VHDL file and the model the same?

It kind of looks like it's loading your top-level VHDL as the HDL Import or vice versa. If so try to make sure that the names do not clash.

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hmmm..im pretty sure there is no clash between the name of the file and the model...