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Altera_Forum's avatar
Altera_Forum
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17 years ago

DSP Builder to ModelSim

Hi , im just perform RTL simulations with the ModelSim software. I add a TestBench block to my DSP builder model. Then I get the following error: # ** Error: (vsim-3817) Formal port "clk" decl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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It might help if you gave a little more information. Does your design compile in Quartus? Does it simulate correctly in Simulink?

Perhaps post a screenshot of your design if not the design (cut down as much as possible to demonstrate the failure) itself.

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thanks for the reply!

yes it compiled smoothly in quartus and run perfectly in simulink. and all the port name mention in the error are from the attached vhdl file.