Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorDSP Builder to ModelSim
Hi , im just perform RTL simulations with the ModelSim software. I add a TestBench block to my DSP builder model. Then I get the following error: # ** Error: (vsim-3817) Formal port "clk" decl...
Altera_ForumHonored Contributor
Honored ContributorI should have clarified it's the name of the entity in the file not the file itself that will clash.
In your original log you have tb_dpt2, which seems to indicate your original model was called dpt2. It also references DSPBuilder_dpt2_import/dpt2.vho, which would indicate you imported a file called dpt2.vhd via HDL Import. Also you might have some stale files around. Try deleting the DSPBuilder_dpt2_import and tb_dpt2 directories and regenerate.
