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Altera_Forum's avatar
Altera_Forum
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17 years ago

DSP Builder 8.0 Advanced Blockset / DSP resources

Has anyone been able to successfully specify that a given FIR filter / NCO / etc. be implemented with logic cells (instead of DSP blocks) in an advanced blockset design? From what I can tell, in the ABS (advanced blockset), you specify a filter type and coeffs (w/ some minimal settings), and then DSP builder infers some things and then synthesizes the module. I know that in a previous version of DSP builder, it basically popped a MegaWizard block when you opened a filter, with the pull-down menus available for what sort of resources to use for coefficient storage, multipliers, etc.

In the situation that I'm in, I'm running out of DSP blocks in my design that has multiple DSP builder blocks. Each of the individual blocks does not know that combining with the other will result in a design too large for the given device. To try and allow the tool to figure this out, I put both of the DSP models into one file (and ran the synthesizer/fitter), but it still overshot the DSP resources (by 15% or so).

The advice from Altera was to target a given module with a DSP_BLOCK_BALANCING assignment.

set_instance_assignment -name DSP_BLOCK_BALANCING "LOGIC ELEMENTS" -to "<instance_name>"

This allows me to build, but I miss timing by multiple ns. I am guessing that when the tool tries to flop out a DSP block for logic cells (after the module has been designed around a DSP implementation), it might make it pretty tough to route. In the previous DSP designs, you would build a MegaWizard block for the FIR (target=logic cells), and then subsequently build the design w/ Signal Compiler.

Anyways, I was hoping that someone might have some input/experience with this sort of situation. I am trying to step through the different blocks in the design that use DSP blocks and seeing if a certain FIR or NCO routes better in logic using the above method, but haven't had much luck.

Thanks,

Jeff

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    One thing you can do is open the Control block at the top of your design. There's a parameter there called Hard Multiplier Threshold which defaults to -1. Setting this to a positive number means that DSPBA will try to replace a multiplier with logic if the number of "LEs" used for it will be less than that number.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thanks for the suggestion. I forgot to mention that I had tried this option previously, with no difference in results. I tried stepping up from 200-300 or so, and currently have the value set to 5000. My understanding of this feature is that if the compiler can implement a given multiply function in less than 5000 logic elements, it will....so it should have tried to build the entire design w/ logic, instead of DSP blocks.

    I don't know if this has something to do with the fact that all of my multipliers in the design are all essentially the same size (18x18). The Altera docs seem to suggest that this is most useful when you have multipliers of varying sizes (i.e. a 4x4 would use a 9x9 DSP block, when the actual number of logic elements to implement would be a lot less than when trying to implement a 9x9 in logic).
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    What you say is correct. If all the multipliers were the same size then they would all be converted to logic at the same time. So you would increase the threshold by 1 and go from 50 DSPs to 0. The threshold becomes a far more useful features if you have many multipliers of different sizes in your design.

    I suspect your actual problem is down to a limitation of the tool. It will only try to convert multipliers if it hasn't already determined to combine them into an alt_multadd.

    If you are using DSPBA to create FIRs, you might be creating the filters in non-constant mode. This could perhaps prevent multipliers from being converted to shifted adder trees which could save you a few multipliers.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I confirmed that they are in constant mode (which was what I intended). The other thing that I'm going to try is to over-clock the design (up to ~360mhz) to see if I can benefit at all from multicycle usage of the DSP blocks to reduce utilization.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Yes if you can set the clock frequency to some integer multiple of the sample rate you should see number of DSPs drop appropriately. (be careful with valid/channel signals)