Driving multiple DDR2 modules

Apart from the question, if the databus capacitive load may be too high, I don't exactly understand the purpose of this circuit. When sharing the databus, why not sharing the other control signals, execpt for chip enable?

As another point, the DDR2 controller cores don't support driving any signal execpt clock to multiple DDIO pins. It would be possible to my opinion, but most likely requires changes to the core code.

The purpose of buffering the address lines & control lines (RAS,CAS,WE) is that as each address/control line goes to each chip you're potentially looking at a load of 16 per module (16 chips/module) x 4 modules=> 64 loads.

The data bus on the otherhand only goes to 2 chips on each module, therefore there is a total load of (2 chips/module )x4 modules=> 8 loads.

Buffering the databus is somewhat more difficult as it's obviously bidirectional and besides I'm not aware of any DDR2 bidirectional buffers.

As for the DDR2 controller I'll write up my own core (as speed isn't an issue it should be fairly straight forward).

Thanks.

The essential point is that all DDR2 signals are generated by DDIO cells, thus buffering would always mean multiplying these DDIO cells rather than adding another buffer. The same can be basically done with bidirectional data, additional limited by the available number of DQ pins. When designing your own core, you should be free to arrange address and data lines according to your needs.

I see the point of high capacitive load, however if it works with two modules at high speeds of 200 MHz and more, it can work with four at 125 MHz.

It might be worth investing in the Mentor Graphics Hyperlinx tool set to model this interface.

Then you will know if it will work or not.

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