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Altera_Forum's avatar
Altera_Forum
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17 years ago

Driving multiple DDR2 modules

Hi, I have an application where we'd like to have a single FPGA driving 4x unbuffered (240 pin) DDR2 memory modules. To keep the FPGA pin count low I'd like to buffer only the Address/Control lines t...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Apart from the question, if the databus capacitive load may be too high, I don't exactly understand the purpose of this circuit. When sharing the databus, why not sharing the other control signals, execpt for chip enable?

As another point, the DDR2 controller cores don't support driving any signal execpt clock to multiple DDIO pins. It would be possible to my opinion, but most likely requires changes to the core code.