Honored Contributor
Honored ContributorThe essential point is that all DDR2 signals are generated by DDIO cells, thus buffering would always mean multiplying these DDIO cells rather than adding another buffer. The same can be basically done with bidirectional data, additional limited by the available number of DQ pins. When designing your own core, you should be free to arrange address and data lines according to your needs.
I see the point of high capacitive load, however if it works with two modules at high speeds of 200 MHz and more, it can work with four at 125 MHz.
