Driving multiple DDR2 modules

The purpose of buffering the address lines & control lines (RAS,CAS,WE) is that as each address/control line goes to each chip you're potentially looking at a load of 16 per module (16 chips/module) x 4 modules=> 64 loads.

The data bus on the otherhand only goes to 2 chips on each module, therefore there is a total load of (2 chips/module )x4 modules=> 8 loads.

Buffering the databus is somewhat more difficult as it's obviously bidirectional and besides I'm not aware of any DDR2 bidirectional buffers.

As for the DDR2 controller I'll write up my own core (as speed isn't an issue it should be fairly straight forward).

Thanks.