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Altera_Forum's avatar
Altera_Forum
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17 years ago

DQ pins limitation of High Performance DDR2 Core

Hi,

When I create a DDR2 Core of High Performance 8.0 which located on the top of the FPGA (StratixII EP2S30F672), and the data bus width is 32 (local bus width = 64, 4 dqs), error occured during Analysis & Synthesis. The Quartus II gave the message that the number of dq pins exceeded the maximum limitation of the DDR2 Core.

Does it means I cannot implement a single High Performance DDR2 Core with 32 dq pins on one side of StratixII?

In my design, I want to extend the data bus width from 16 to 32 using two 16bits DDR2 chip, and control the two DDR2 chip using only one High Performance Core. How can I achieve it?

Another question: Does the High Performance Core always occupies 1 Enhanced PLL instead of Fast PLL?

Thanks a lot!

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Perhaps it would be more beneficial if you actually posted the error that Quartus is giving you. The DDR2 core is certainly capable of handling a 32-bit interface. It may be that your device (EP2S30F672) doesn't have the capacity on one side of the chip.

    The DDR2 core requires a PLL. It can be either enhanced or fast I believe.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Well I just did a test compile using the ddr2 example project. I was able to get the entire DDR2 interface onto one side of the chip (the bottom).

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Thank you!

    I want to instantiate the HP Core on the top of the FPGA device.

    The error I mentioned above is:

    Error: Delayctrlout port of DLL "ddr2:inst|ddr2_controller_phy:ddr2_controller_phy_inst|ddr2_phy:alt_mem_phy_inst|ddr2_phy_alt_mem_phy_sii:ddr2_phy_alt_mem_phy_sii_inst|ddr2_phy_alt_mem_phy_clk_reset_sii:clk|dll" feeds 4 DQS I/O pins that feed 32 DQ I/O pins. A maximum of 21 DQ I/O pins can be associated with single DLL.

    But, when I created another HP Core with the presets settings for Micron device (data bus = 72 and local bus = 144), the error above changed to "A maximum of 50 DQ I/O pins can be associated with single DLL."

    I am confused. If the maximum DQ I/O pins associated with single DLL is 50, why can't I instantiate a HP Core with 32 DQ I/O pins?

    Hope you to release me.:D :D