DQ pins limitation of High Performance DDR2 Core

Thank you!

I want to instantiate the HP Core on the top of the FPGA device.

The error I mentioned above is:

Error: Delayctrlout port of DLL "ddr2:inst|ddr2_controller_phy:ddr2_controller_phy_inst|ddr2_phy:alt_mem_phy_inst|ddr2_phy_alt_mem_phy_sii:ddr2_phy_alt_mem_phy_sii_inst|ddr2_phy_alt_mem_phy_clk_reset_sii:clk|dll" feeds 4 DQS I/O pins that feed 32 DQ I/O pins. A maximum of 21 DQ I/O pins can be associated with single DLL.

But, when I created another HP Core with the presets settings for Micron device (data bus = 72 and local bus = 144), the error above changed to "A maximum of 50 DQ I/O pins can be associated with single DLL."

I am confused. If the maximum DQ I/O pins associated with single DLL is 50, why can't I instantiate a HP Core with 32 DQ I/O pins?

Hope you to release me.:D :D