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Altera_Forum
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17 years ago

DQ pins limitation of High Performance DDR2 Core

Hi, When I create a DDR2 Core of High Performance 8.0 which located on the top of the FPGA (StratixII EP2S30F672), and the data bus width is 32 (local bus width = 64, 4 dqs), error occured dur...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Well I just did a test compile using the ddr2 example project. I was able to get the entire DDR2 interface onto one side of the chip (the bottom).