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Altera_Forum
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17 years ago

DQ pins limitation of High Performance DDR2 Core

Hi, When I create a DDR2 Core of High Performance 8.0 which located on the top of the FPGA (StratixII EP2S30F672), and the data bus width is 32 (local bus width = 64, 4 dqs), error occured dur...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Perhaps it would be more beneficial if you actually posted the error that Quartus is giving you. The DDR2 core is certainly capable of handling a 32-bit interface. It may be that your device (EP2S30F672) doesn't have the capacity on one side of the chip.

The DDR2 core requires a PLL. It can be either enhanced or fast I believe.

Jake