Altera_Forum
Honored Contributor
8 years agoDDR3 memory controller Termination calibration error.
Hi,
I am using DDR3 memory controller generated with UniPhy IP core, for Cyclone V device. I have selected 'No sharing' mode for OCT sharing option. Also connected oct_rzqin port to the input pin. But tool issues the following error when I run Analysis & Synthesis. Error (15700): Termination calibration block atom "ddr3_mem_controller:DDR3_CONTROLLER_BOT|ddr3_mem_controller_0002:ddr3_mem_controller_inst|altera_mem_if_oct_cyclonev:oct0|sd1a_0" uses RZQIN port, which must be connected to a dedicated I/O atom with no other fanout From the error message I undestood that oct_rzqin port should be connected to the dedicated I/O pin. But I have added pin lock constraint for these pin in my qsf file. I have no idea why still tool issues this error. Looking for the help from here. Thanks in advance.