Altera_ForumHonored Contributor8 years agoDDR3 memory controller Termination calibration error. Hi, I am using DDR3 memory controller generated with UniPhy IP core, for Cyclone V device. I have selected 'No sharing' mode for OCT sharing option. Also connected oct_rzqin port to the input p...Show More
Recent DiscussionsError when simulating F-tile Ethernet example designAvalon Transaction Responses & BridgesSerialLite II license for Arria10 FPGAAgilex3/5 GTS Hard Ethernet IP 10G example design pin loc and io std wantedCORDIC ATan2 Failed to Generate