ddr2 sdram

these parameters refer to timing parameters for the DDR2 you actually have in your kit. so you have to read the corresponding data sheet of the DDR2 and fill in the blanks!

I recommend to take the "standard" design as a starting point.

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these parameters refer to timing parameters for the DDR2 you actually have in your kit. so you have to read the corresponding data sheet of the DDR2 and fill in the blanks!

I recommend to take the "standard" design as a starting point.

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Thank you for your reply.

I find that the "standard" project is built in Quartus5,but I am using Quartus9.

I build a simplest project, it only contain Nios II CPU + jtag uart + ddr2 sdram, and fill the dd2 sdram's parameters as the "standard" dose.

But I get this error message when I compile my project:

Following DDIO Output nodes could not be placed by the Fitter

Now I don't know how to deal with this error

adream307@gmail.com

I am happy to tell you that I am using the same board that you have!

Anyway, to deal with old versions you would only open the SOPC Builder and chose to upgrade the design and then continue using your version normally.

Tell me what assignment did you use for the DDR2 pins? I think that you assigned them using the ep2c70f672 board location while you must use the original ddr2 core location (Refers to the reference manual of the board.)

I again recommend to use the standard design which comes with the board documents (<..>\Kits\CycloneII_DSP_Kit-v6.0.1\Examples\NiosII\example_designs\verilog). The design has its correct assignment and any other parametrization.

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I am happy to tell you that I am using the same board that you have!

Anyway, to deal with old versions you would only open the SOPC Builder and chose to upgrade the design and then continue using your version normally.

Tell me what assignment did you use for the DDR2 pins? I think that you assigned them using the ep2c70f672 board location while you must use the original ddr2 core location (Refers to the reference manual of the board.)

I again recommend to use the standard design which comes with the board documents (<..>\Kits\CycloneII_DSP_Kit-v6.0.1\Examples\NiosII\example_designs\verilog). The design has its correct assignment and any other parametrization.

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Thank you very much ^_^

I surprise to find that I can build the "standard" project after upgrade,and I can run the "hello world" program in "standard".

Then I remove unused components,the only left components are cpu, epcs controller,jtag,on chip memory and ddr2 sdram.

After these actions, I rebuild the "standard",I find that "hello world" program can still run on this cutted "standard".

Now I create a project , it contain cpu,epcs controller,jtag,on chip memory and ddr2 sdram,all the parameters is same as the "standard",and write an top module using verilog language not by a .bdf file.

I can compile my project successfully,but when I run "hello world" program on this cpu,I get this information:

Verifying 04000000 ( 0%)

Verify failed between address 0x4000000 and 0x400E243

Leaving target processor paused

Thank you:)

I am glad to know that I could give help.

I don't exactly know why that error occurs, anyway you should not leave the standard design and just apply your modifications on it cause the project has its own constrains (refer to Assignments > Assignment Editor > Categories > Timing.)

good luck

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I am glad to know that I could give help.

I don't exactly know why that error occurs, anyway you should not leave the standard design and just apply your modifications on it cause the project has its own constrains (refer to Assignments > Assignment Editor > Categories > Timing.)

good luck

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I am happy to tell you that I have solved my problem.

The clock for ddr2 sdram controller has 0 degree phase,but the clock for ddr2 sdram write has -90 degree

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are you using the DDR2 with it's full scale (256 MB)?

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No, In my project, all the parameters are the same as "standar",so the memory data bus width is 16.

But when I change the memory data bus width to 64,I confront the same error message:

Following DDIO Output nodes could not be placed by the Fitter

When I assign my pins as you advised, I still get this error.

I could raise the memory size to 128MB, and there was no error like what you said, maybe you should re-assure the assignments!

Anyway I am stuck with using the full size which is 256MB, the memtest fails there.

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I could raise the memory size to 128MB, and there was no error like what you said, maybe you should re-assure the assignments!

Anyway I am stuck with using the full size which is 256MB, the memtest fails there.

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When setting the parameters of ddr2 sdram controller in sopc build, I don't know how to deal with "constraints",I don't what's "constraints" mean?

Thank you