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I am happy to tell you that I am using the same board that you have!
Anyway, to deal with old versions you would only open the SOPC Builder and chose to upgrade the design and then continue using your version normally.
Tell me what assignment did you use for the DDR2 pins? I think that you assigned them using the
ep2c70f672 board location while you must use the
original ddr2 core location (Refers to the
reference manual of the board.)
I again recommend to use the standard design which comes with the board documents (<..>\Kits\CycloneII_DSP_Kit-v6.0.1\Examples\NiosII\example_designs\verilog). The design has its correct assignment and any other parametrization.
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Thank you very much ^_^
I surprise to find that I can build the "standard" project after upgrade,and I can run the "hello world" program in "standard".
Then I remove unused components,the only left components are cpu, epcs controller,jtag,on chip memory and ddr2 sdram.
After these actions, I rebuild the "standard",I find that "hello world" program can still run on this cutted "standard".
Now I create a project , it contain cpu,epcs controller,jtag,on chip memory and ddr2 sdram,all the parameters is same as the "standard",and write an top module using verilog language not by a .bdf file.
I can compile my project successfully,but when I run "hello world" program on this cpu,I get this information:
Verifying 04000000 ( 0%)
Verify failed between address 0x4000000 and 0x400E243
Leaving target processor paused
Thank you:)
Honored Contributor
