Hi Aaron,
May I confirm whether the DDR2 IP license was purchased together with other licenses, or as a standalone license?
Based on the licensing behavior, a valid DDR license is not subject to time limitation. The time limitation only applies to FPGA IP Evaluation Mode, where Quartus generates a time-limited programming file (*_time_limited.sof).
For your project,
- Quartus generates project.sof successfully.
- No project_time_limited.sof file is generated.
This behavior indicates that the DDR2 IP is being compiled with a valid, unrestricted license rather than an evaluation license. As a result, there are no project_time_limited.sof which will expires within certain time limit is present.
For your reference, I have attached a screenshot from the Altera FPGA IP Software Installation and licensing documentation that describes the licensing behavior of FPGA IP cores (https://docs.altera.com/r/docs/683472/25.3/altera-fpga-software-installation-and-licensing/questa-altera-fpga-edition-and-questa-altera-fpga-starter-edition-software-license)

As an additional check, the customer can review the Quartus compilation log for any OpenCore Plus or time-limited core messages, which would indicate that an IP in the design is running in evaluation mode.
Thank you.!
Regards,
ZiYingE_Altera