Forum Discussion
Honored ContributorData send thru ethernet
Hello,
I am trying to do a simple task: I will form an UDP packet in hardware, then I want to move it to Nios, add IP header and send to ethernet. I will split my problem into two parts: I've created avalon streaming source component, so I am able to move the packet to the Nios memory using SGDMA stream to memory, however I am not sure how can I move the packet to the TSE core? TSE also use SGDMA (st-to-mem and mem-to-st), so I can't connect my component to one of those SGDMA inputs, since it is already in use. What are my options? Add another SGDMA Stream-to-memory core and connect to the same memory that TSE SGDMA use? How can I pick the data from the memory using another SGDMA there? Lets say I already have a packet data in Nios, how can I add IP header to the packet using InterNiche? Maybe there are some examples of packet generation using InterNiche? Also I can't find NicheStack documentation anywhere, maybe someone could point me out? I suppose simple packet sending or receiving tasks can be used without RTOS? I have chosen SGDMA because the data stream can reach 50mbps or more, so the Nios should be really fast to add a header to the whole packet, which is almost 1400 bytes. Thank You.38 Replies
Altera_ForumUse sendto() function. For instance,
l = sendto(conn->fd, data, pkgLth, 0,(struct sockaddr *)&cliaddr,nLen); By the by can you tell me how you move the data from hardware to Nios processor? Jacky- Altera_Forum
Maybe there is documentation for all the stack?
I am using my custom hardware->Avalon-ST and Avalon-ST-> hardware component. They're very simple to do, since SOPC builder gives templates, when creating a new component. - Altera_Forum
That's socket programming. I'm not sure if altera has such a document but you can find them in C socket programming template
- Altera_Forum
Since you started generating the udp packet in hardware, why don't you go all the way and generate the IP and Ethernet headers the same way? Then you can use a multiplexer and send your packet directly to the TSE without going through memory.
Did you have a look at the UDP offload example? http://www.alterawiki.com/wiki/nios_ii_udp_offload_example - Altera_Forum
Hm, I am not sure, but I suppose IP header is a bit harder to add in hardware, because of header checksum. Maybe there are full (IP(UDP(RTP))) implementations in hardware?
I am checking UDP offload example now, too bad I am bad at verilog :) - Altera_Forum
The payload checksum in UDP is optionnal, so indeed you are only left with the IP header cheksum. If all your packets have the same length, the checksum will always be the same and can be pre-calculated in software. If your packets have various length, the software can pre-calculate the checksum with a length of 0 and the hardware just needs to add the length to that value before putting it in the header. I don't remember how this is done in the example.
The Ethernet CRC is automatically calculated by the TSE so you don't need to worry about this one. - Altera_Forum
What about packet receive then? In this phase, I do only transmit, but in the second I will have to do packet receive. My idea was to make header easy to add/check/remove.
Altera provides Video-Over-IP reference design, which is exactly what I need, however I did not manage to make it running on Q10.1sp1, so I am doing my own. - Altera_Forum
I think the offload example shows how to do the receive part too.
- Altera_Forum
Ok I will check it, thanks.
- Altera_Forum
The old design made with Q9.0 fails timing @ 10.1sp1, so the design doesn't run - Nios is not found in the system (yes, sysid component is in the system). I've checked the source, however such simple project it should be, but use RTOS - which makes it complicate...
