Cyclone 10 GX: How to implement DDR I/O and BUFGCE equivalent in Quartus?
Hello,
I am working on a design using Cyclone 10 GX and need to implement two functionalities:
1. **Basic DDR (Double Data Rate) I/O**:
In Intel's older devices, primitives like ALTDDIO_IN, ALTDDIO_OUT, or ALTDDIO_BIDIR were available for simple DDR I/O operations. However, I noticed that these IPs are not supported in Cyclone 10 GX. Is there a recommended way or equivalent IP/primitive in Quartus for implementing basic DDR I/O on FPGA pins? My use case is to send and receive DDR data on pins, not to interface with external DDR memory.
2. **Global Clock Enable (BUFGCE equivalent)**:
In Xilinx devices, I often use the BUFGCE primitive to dynamically enable or disable global clocks. Is there an equivalent feature, primitive, or IP in Quartus for Cyclone 10 GX to achieve similar functionality?
Any guidance, examples, or documentation references would be greatly appreciated. Thank you!