New Contributor
Super ContributorFor the clocks, you use the altclkctrl block to use global enable on a clock domain: https://www.intel.com/content/www/us/en/docs/programmable/683775/current/clock-control-block.html.
New ContributorThank you for clarifying that altclkctrl can be used for global clock enable functionality similar to BUFGCE. That answers my question about clock control.
Now, I would like to implement **IDDR (Input Double Data Rate) and ODDR (Output Double Data Rate)** functionality in Cyclone 10 GX.
In Xilinx devices, IDDR and ODDR primitives are commonly used for DDR data transfer on I/O pins. Is there an equivalent IP core, primitive, or recommended method in Intel Quartus for implementing similar DDR functionality on Cyclone 10 GX?
If no direct IP or primitive is available, are there examples or guidelines for manually implementing DDR I/O using Cyclone 10 GX resources?
Thank you for your help!
