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New ContributorCXL Example Design simulation: Illegal combination of drivers
Hi,
Running the simulation of the CXL Example Design, following the CXL_Reference_Designs_User_Guide_v1.5.pdf document, gives the following errors during elaboration:
Error-[ICPD_INIT] Illegal combination of drivers
The same error is caught on the following files:
cxltyp3ddr_tb_22p3/run/qpds_ed_rtl_t3ip//intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_100/sim/cxl_memexp_sip_rst_ctrl.sv, 23
cxltyp3ddr_tb_22p3/run/qpds_ed_rtl_t3ip//intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_100/sim/bbs_wrapper.sv, 23
cxltyp3ddr_tb_22p3/run/qpds_ed_rtl_t3ip//intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_100/sim/bbs_top.sv, 23
cxltyp3ddr_tb_22p3/run/qpds_ed_rtl_t3ip//intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_top_100/sim/cxl_io_top.sv, 23
cxltyp3ddr_tb_22p3/run/qpds_ed_rtl_t3ip//intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_ast_100/sim/soft_wrapper/rnr_cxl_rx_aib_deskew_sm.sv, 24
cxltyp3ddr_tb_22p3/run/qpds_ed_rtl_t3ip//intel_rtile_cxl_top_cxltyp3_ed/intel_rtile_cxl_ast_100/sim/soft_wrapper/rnr_cxl_reset_ctrl.sv, 24
All these 6 files are encrypted, so it is not possible to confirm if the violation is real.
The environment uses:
Quartus 2.23 (also tried with 2.24, but got the same result)
Synopsys VCS T-2022.06-SP2-1
Avery BFM v2.5
Has anyone encountered the same situation? Any suggestions on how to debug the issue?
Thank you,
Ricardo.
32 Replies
JohnT_AlteraRegular Contributor
Hi Ricardo,
Can you try based on V1.7 user guide (https://cdrdv2.intel.com/v1/dl/getContent/763513?explicitVersion=true&wapkw=cxl)? If you are still seeing issue, can you provide me the error message?
RicardoCOccasional Contributor
Hi John,
I still see the same issues using version 1.7 of the document. However, I'd like to point out that I modified some files to dump waveforms using VPD (APCI_DUMP_VPD), instead of FSDB (APCI_DUMP_FSDB), since we don't currently have Verdi. I'm not sure this is the reason why I'm getting the "Error-[ICPD_INIT] Illegal combination of drivers" messages.
I'm attaching the log files for your reference.
In case the lack of Verdi was the reason behind the elaboration failure, would there be anything that I could do to simulate without it?
Thank you,
Ricardo.
- JohnT_Altera
Hi,
Unfortunately there is no way to simulate without the Verdi.
- RicardoC
Thank you.
- RicardoC
Hi John,
We acquired a license of Verdi and the elaboration fails with 24 errors of the type:
Error-[CFCILFBI] Cannot find cell in liblist
The environment is using the following tools and versions:
Quartus 2.24
Synopsys VCS T-2022.06-SP2-1
Avery BFM v2.5
Synopsys Verdi T-2022.06-SP2-1
CXL_DE_User_Guide_v1.7.pdfI have attached the log files for your reference. Do you have any recommendations?
Thank you,
Ricardo.
- JohnT_Altera
Hi,
From the error it looks like it is not able to link Quartus IP library. Can you check your environment to see if the "QUARTUS_INSTALL_DIR" and "QUARTUS_LIB_DIR" is set correctly? Or do you have the Quartus license setup correctly?
- RicardoC
Hi John,
QUARTUS_INSTALL_DIR and QUARTUS_LIB_DIR are set to Quartus' installation path from root:
$ set | grep QUARTUS
QUARTUS_INSTALL_DIR=/shared/opt/intel/intelFPGA_pro/22.4/quartus
QUARTUS_LIB_DIR=/shared/opt/intel/intelFPGA_pro/22.4/quartusIf I modify from these values, vcs_sim.sh fails in the compilation phase, as it cannot find the source files to compile.
LM_LICENSE_FILE is pointing to:
$ set | grep LM
LM_LICENSE_FILE=4071@licmgr:27020@licmgr:/shared/opt/intel/licenses/LR-107633_License.dat4071@licmgr is for Avery, 27020@licmgr is for VCS and Verdi, and LR-107633_License.dat is for Quartus.
Any other suggestion?
Thank you,
Ricardo.
- JohnT_Altera
Hi,
Can you double confirm the directory is correct? May I know what is the changes made?
- RicardoC
Hi John,
I ran "which quartus", and I got the following:
[cxltyp3ddr_tb_22p4]$ which quartus
/shared/opt/intel/intelFPGA_pro/22.4/quartus/bin/quartus
[cxltyp3ddr_tb_22p4]$ set | grep QUARTUS
QUARTUS_INSTALL_DIR=/shared/opt/intel/intelFPGA_pro/22.4/quartus
QUARTUS_LIB_DIR=/shared/opt/intel/intelFPGA_pro/22.4/quartus
[cxltyp3ddr_tb_22p4]$Can you confirm if these are correct?
Can you be more specific on which changes you are referring to?
Thank you,
Ricardo.
OliverJacob12
@RicardoC wrote:
Hi John,
I ran "which quartus", and I got the following:
[cxltyp3ddr_tb_22p4]$ which quartus
/shared/opt/intel/intelFPGA_pro/22.4/quartus/bin/quartus
[cxltyp3ddr_tb_22p4]$ set | grep QUARTUS
QUARTUS_INSTALL_DIR=/shared/opt/intel/intelFPGA_pro/22.4/quartus
QUARTUS_LIB_DIR=/shared/opt/intel/intelFPGA_pro/22.4/quartus
[cxltyp3ddr_tb_22p4]$Can you confirm if these are correct?
Can you be more specific on which changes you are referring to?
Thank you,
Ricardo.
Could you please share the procedure to run the design example using VCS Mx instead of VCS?
- JohnT_Altera
Hi,
The setting looks correct. Are you observing same error where it is not able find the IP?
- RicardoC
Hi,
Yes. The same messages of the type:
Error-[CFCILFBI] Cannot find cell in liblist
/fpga/cxltyp3ddr_tb_22p4/run/qpds_ed_rtl_t3ip//intel_rtile_cxl_top_cxltyp3_ed/altera_iopll_1931/sim/intel_rtile_cxl_top_cxltyp3_ed_altera_iopll_1931_lsetw4a.vo, 270
Cell 'tennm_iopll' cannot be found in liblist for binding instance
'cxl_tb_top.dut.intel_rtile_cxl_top_inst.intel_rtile_cxl_top_0.cxl_memexp_sip_top.gen_clkrst.cxl_memexp_sip_clkgen.rnr_ial_sip_clkgen_pll.tennm_pll'.
Liblist: TB_LIB AVMM_INTERCONNECT LIB_T3IP LIB_CXLIP_LIB DEFAULT
Config rule:
"/fpga/cxltyp3ddr_tb_22p4/tb/verif/tb_top/cxl_tb_top_config.sv",
61: default liblist tb_lib avmm_intercon ...
Source Info: tennm_iopll #(.auto_clk_sw_en("false"), .bw_mode("low_bw"),
.c0_bypass_en("true"), .c0_even_duty_en("false"), .c0_high(256),
.c0_low(256), .c0_out_en(counter0 ...I don't see any errors during the compilation, so it seems that whatever is missing should be coming a pre-compiled library. (?)
Is it correct to set env variables QUARTUS_INSTALL_DIR and QUARTUS_LIB_DIR to the same directory?
Thanks,
Ricardo.
- JohnT_Altera
Hi,
Are you running "sh ./vcs_sim.sh ./cxl_ed/intel_rtile_cxl_top_0_ed" command to run the simulation?
- RicardoC
Hi,
The Quartus output is not under the testbench directory, but it's called with its absolute path:
sh ./vcs_sim.sh /shared/proj/work/quartus/cxltype3/intel_rtile_cxl_top_0_ed
Does the Quartus output have to be under the testbench directory?
Thanks,
Ricardo.
- RicardoC
Hi John,
I just copied the Quartus output to under the tb directory and it still fails with the same messages.
Thanks,
Ricardo.
- JohnT_Altera
Hi,
Please do not copy the output folder and have it link to the original directory.
- RicardoC
Hi John,
I was wondering if you could upload the log files from your working run. This way I can compare against mine and check if there is any discrepancies.
Thank you,
Ricardo.
- JohnT_Altera
Hi,
Can you trying adding "setenv ELAB_PARAM_DEFINES "-ignore initializer_driver_checks"" to see if you are able to move forward?
- RicardoC
Hi John,
After setting the environment variable, the outcome is still the same. Note that the "-ignore initializer_driver_checks" parameter is set in the elaboration log file:
Command: vcs +vcs+lic+wait cxl_tb_top_config +plusarg_save +vcs+lic+wait -full64 \
+vcs+nostdout -kdb -lca -assert enable_diag -assert svaext -o /fpga/cxltyp3ddr_tb_22p4/run/simv \
+lint=TFIPC-L +lint=PCWM +warn=noSVA-LDRF -j4 -P /shared/opt/synopsys/verdi/T-2022.06-SP2-1/share/PLI/VCS/LINUX/novas.tab \
+warn=noLCA_FEATURES_ENABLED +warn=noDFLT_OPT +warn=noSVA-TIDE +warn=noOSVF-NPVIUFPI \
+warn=noUFTMD +error+1000 -debug_access+all+classdbg+f -debug_region=lib+cell -CFLAGS \
-DVCS /shared/opt/synopsys/vcs/T-2022.06-SP2-1/etc/uvm-1.2/src/dpi/uvm_dpi.cc -ignore \
initializer_driver_checks /shared/opt/avery/2.5a/avery_pli-2023_0202/lib.linux/libtb_vcs64.a \
-P /shared/opt/avery/2.5a/avery_pli-2023_0202/tb_vcs64.tab -l /fpga/cxltyp3ddr_tb_22p4/run/elab.log \I have attached the complete elaboration log file for your reference.
Thanks,
Ricardo.
