RicardoC
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CXL IP for Device Type3 (feature 6AF7 0188) license fails to generate sof
A newly generated license file doesn't allow a previously successful database build to produce an sof file. The license manager log file states the required feature was successfully checked out, and checked in, but quartus_asm doesn't agree with it. The license manager, and the Quartus versions are both 23.3. Running lmdiag on the feature also confirms that it is available on the same machine running quartus_asm. The following is the output of quartus_asm and lmdiag: [user@supermicro2 hardware_test_design]$ quartus_asm --read_settings_files=on --write_settings_files=off cxltyp3_memexp_ddr4_top -c cxltyp3_memexp_ddr4_top Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 23.3.0 Build 104 09/20/2023 SC Pro Edition Info: Copyright (C) 2023 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the Intel FPGA Software License Subscription Agreements Info: on the Quartus Prime software download page. Info: Processing started: Mon Jul 8 17:32:32 2024 Info: System process ID: 1431063 Info: Command: quartus_asm --read_settings_files=on --write_settings_files=off cxltyp3_memexp_ddr4_top -c cxltyp3_memexp_ddr4_top Info: The application is running in 'DNI' mode. Info (16677): Loading final database. Info (16734): Loading "final" snapshot for partition "root_partition". Info (16734): Loading "final" snapshot for partition "auto_fab_0". Info (16678): Successfully loaded final database: elapsed time is 00:00:26. Info (22889): This design was generated using the DNI flow. Error (23714): Can not generate programming files for your current project because you do not have a valid license. Visit the Intel FPGA Self-Service Licensing Center at https://licensing.intel.com Warning (115005): Unlicensed IP: "CXL IP for Device Type3 with DDR4 based MemBuffer (6AF7 0188)" Warning (115004): Unlicensed encrypted design file: "/proj/hardware_test_design/qdb/_compiler/cxltyp3_memexp_ddr4_top/root_partition/23.3.0/final/1/netlist.model" Warning (115004): Unlicensed encrypted design file: "/proj/hardware_test_design/qdb/_compiler/cxltyp3_memexp_ddr4_top/auto_fab_0/23.3.0/final/1/names.model" Warning (115004): Unlicensed encrypted design file: "/proj/hardware_test_design/qdb/_compiler/cxltyp3_memexp_ddr4_top/auto_fab_0/23.3.0/final/1/netlist.model" Warning (115004): Unlicensed encrypted design file: "/proj/hardware_test_design/qdb/_compiler/cxltyp3_memexp_ddr4_top/root_partition/23.3.0/final/1/names.model" Error: Quartus Prime Assembler was unsuccessful. 1 error, 5 warnings Error: Peak virtual memory: 7791 megabytes Error: Processing ended: Mon Jul 8 17:33:22 2024 Error: Elapsed time: 00:00:50 Error: System process ID: 1431063 [user@supermicro2 hardware_test_design]$ /tools/intel/intelFPGA_pro/23.3/quartus/linux64/lmutil lmdiag -c 1800@licmgr 6AF7_0188 lmutil - Copyright (c) 1989-2021 Flexera. All Rights Reserved. FlexNet diagnostics on Mon 7/8/2024 17:33 ----------------------------------------------------- License file: 1800@licmgr ----------------------------------------------------- "6AF7_0188" v2024.10, vendor: alterad, expiry: 06-oct-2024 vendor_string: iiiiiiiihdLkhMMMMMMMMUPDuiSSSSSSSS11X38oooooooopjz5cqqqqqqqqtmGzGEEEEEEEEbqIh0qqqqqqqqgYYWiHHHHHHHHbp0FVwwwwwwwwBUEakyyyyyyyyD2FFRllllllllWL$84 License server: licmgr floating license expires: 06-oct-2024 This license can be checked out ----------------------------------------------------- [user@supermicro2 hardware_test_design]$ Any suggestions on how to address the situation? Thank you, Ricardo3.7KViews0likes4CommentsRe: CXL IP Debug Toolkit
Hi WZ, I hope are recovering well. The document that you pointed to has the CXL registers addresses. It does not provide any information on the debug registers that the Debug Toolkit outputs. We are using the original pof image shipped by Intel. Regards, Ricardo3KViews0likes0CommentsRe: CXL IP Debug Toolkit
Hi WZ, The issue evolved into 2 phases of debugging. The first, and original, situation was the failure to boot the OS in the AMD system. With the Intel CXL Type 3 Example Design image in the DK-DEV-AGI027R1BES development kit plugged into the system, the handoff from firmware (EFI) boot to the OS causes the system to reboot itself. It happens in a very early stage of the boot, so no logs are created by the OS. By forcing the CXL to be treated as Special Purpose Memory in the BIOS settings, the OS is able to boot, but the device is not seen as a CXL device. Which leads to phase 2 of the investigation. In the second situation, as stated earlier, the OS is able to boot, but the card does not appear as a CXL device to the OS. daxctl is invoked in order to make the device usable to the OS as a memory one. A simple C program was written so that a single byte can be written to the device. However, as soon as the write operation is executed, the system reboots itself. The file attached to the start of the thread shows the CXL IP registers status extracted using the Debug Toolkit, after the write has been executed and the system rebooted. Could you provide details on the meaning of the Debug Toolkit registers? Thank you, Ricardo3.2KViews0likes0CommentsCXL IP Debug Toolkit
Hello, An Intel development kit DK-DEV-AGI027R1BES with the CXL Type 3 Example Design image causes an AMD Siena architecture system to reboot when a single write is issued. The information extracted by the Debug Toolkit seems to point to failures, but the documentation does not give details on the description of the registers. The most notable entries are: Local Retry State Machine,0x8c00 Num Local CRC Detected,0x2 Local FSM State Status,0x3 Viral Log,0x4 Link Received Viral,0x1 BBS Idle Status,0x0 BBS Error Status,0x1 BBS CXL Status Register Slice0,0xc0000000 BBS Error Status Register,0x12 Device Protocol Table Error,0x1 M2S Viral Received,0x1 BBS Error Status First Register,0x10 The counters show some interesting results. Even though a single Byte RwD was requested by the application, a Req also happened, and apparently only the Req was responded with DRS, whereas the RwD didn't trigger NDR to be sent: Counter of M2SReq Operations,0x1 M2SReq Counter,0x1 Counter of M2SRwD Operations,0x1 M2SRwD Counter,0x1 Counter of S2MDRS Operations,0x1 S2MDRS Counter,0x1 Counter of S2MNDR Operations,0x0 S2MNDR Counter,0x0 Is there more information available on the meaning of the registers for the CXL IP Debug Toolkit? Thank you, Ricardo PS: The complete dump of registers from the Debug Toolkit can be found attached.3.2KViews0likes8CommentsRe: Enabling HPS JTAG on DK-DEV-AGI027RBES
Hi Jingyang, I have not been able to test it because the reference design used in the released document makes use of an Ethernet controller, a Nios V and some other 3 IPs that we don't have license for. I will update this thread when I'm able to try it. Thank you, Ricardo.1.7KViews0likes0Comments- 1.9KViews0likes0Comments