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JHaye4's avatar
JHaye4
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Constraints warning from async_clock_corsser

I am using a QSYS in my design and get the following warnings when compiling. I am instantiating a clock, constraining it correctly, and feeding it to the QSYS so I'm not sure what is going on.

Warning(17897): No destination clock period was found satisfying the set_net_delay assignment from "[get_registers {i_sys_f1_wrap|i_sys_f1|mm_interconnect_1|crosser_003|async_clock_crosser.clock_xer|out_data_toggle_flopped}]" to "[get_registers {i_sys_f1_wrap|i_sys_f1|mm_interconnect_1|crosser_003|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]". This assignment will be ignored. 
Warning(17897): No destination clock period was found satisfying the set_net_delay assignment from "[get_registers {i_sys_f1_wrap|i_sys_f1|mm_interconnect_1|crosser_004|async_clock_crosser.clock_xer|out_data_toggle_flopped}]" to "[get_registers {i_sys_f1_wrap|i_sys_f1|mm_interconnect_1|crosser_004|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]". This assignment will be ignored. 
Warning(17897): No destination clock period was found satisfying the set_net_delay assignment from "[get_registers {i_sys_f1_wrap|i_sys_f1|mm_interconnect_1|crosser_002|async_clock_crosser.clock_xer|in_data_toggle}]" to "[get_registers {i_sys_f1_wrap|i_sys_f1|mm_interconnect_1|crosser_002|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]". This assignment will be ignored. 
Warning(17897): No destination clock period was found satisfying the set_net_delay assignment from "[get_registers {i_sys_f1_wrap|i_sys_f1|mm_interconnect_1|crosser_005|async_clock_crosser.clock_xer|out_data_toggle_flopped}]" to "[get_registers {i_sys_f1_wrap|i_sys_f1|mm_interconnect_1|crosser_005|async_clock_crosser.clock_xer|out_to_in_synchronizer|din_s1}]". This assignment will be ignored. 
Warning(17897): No destination clock period was found satisfying the set_net_delay assignment from "[get_registers {i_sys_f1_wrap|i_sys_f1|mm_interconnect_1|crosser|async_clock_crosser.clock_xer|in_data_toggle}]" to "[get_registers {i_sys_f1_wrap|i_sys_f1|mm_interconnect_1|crosser|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]". This assignment will be ignored. 
Warning(17897): No destination clock period was found satisfying the set_net_delay assignment from "[get_registers {i_sys_f1_wrap|i_sys_f1|mm_interconnect_1|crosser_001|async_clock_crosser.clock_xer|in_data_toggle}]" to "[get_registers {i_sys_f1_wrap|i_sys_f1|mm_interconnect_1|crosser_001|async_clock_crosser.clock_xer|in_to_out_synchronizer|din_s1}]". This assignment will be ignored. 
Warning(17897): No destination clock period was found satisfying the set_net_delay assignment from "[get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]" to "[get_registers {i_sys_f1_wrap|i_sys_f1|mm_interconnect_1|crosser|async_clock_crosser.clock_xer|out_data_buffer*}]". This assignment will be ignored. 
Warning(17897): No destination clock period was found satisfying the set_net_delay assignment from "[get_registers {*altera_avalon_st_clock_crosser:*|in_data_buffer*}]" to "[get_registers {i_sys_f1_wrap|i_sys_f1|mm_interconnect_1|crosser_002|async_clock_crosser.clock_xer|out_data_buffer*}]". This assignment will be ignored.
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    5 years ago

    Hi James,


    I received the feedback from engineering. These warnings can be safely ignored. You may also use the sdc that I emailed to you to fix the warning.


    Thanks

    Best regards,

    KhaiY


9 Replies

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Thanks for sharing the design. Please allow me some time to look into this.


    Thanks

    Best regards,

    KhaiY


    • JHaye4's avatar
      JHaye4
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Did you have any luck?

      Thank you very much,
      James

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi James,


    I can reproduce the warning and I filed a case to our engineering team for investigation. However, I have yet to receive the reply from the team. I shall come back to you once I receive the feedback from the team.


    Thanks

    Best regards,

    KhaiY


  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi James,


    I received the feedback from engineering. These warnings can be safely ignored. You may also use the sdc that I emailed to you to fix the warning.


    Thanks

    Best regards,

    KhaiY


    • JayHarikumaran's avatar
      JayHarikumaran
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      Hello KhaiY,

      I am also receiving the same error as listed in the original post. I am using quartus prime lite 21.1. Could I ignore these warnings and assume that the constraint is actually implemented in the timing based compilation?

      Regards

      Jay

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Which software edition (Pro/Standard) and version you are using? Could you share the design and steps to reproduce the error?


    Thanks

    Best regards,

    KhaiY


    • JHaye4's avatar
      JHaye4
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      I am using Quartus Pro 19.4. I have attached my qsys design that is in question.

      I made sure to connect the inputs and outputs of the Qsys to pins in my top level module so that they are not synthesised away, all clock pins are being driven correctly. There is no real further logic in my top level module so I have not included it.

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Error below occurred during QSYS HDL generation.

    Error: sys_f1_amm_conduit_fl_24b_0.amm_conduit_fl_24b_0: Component amm_conduit_fl_24b 1.0 not found or could not be instantiated

    Error: qsys-generate failed with exit code 3: 1 Error, 5 Warnings

    Error: sys_f1_amm_conduit_fl_24b_0.amm_conduit_fl_24b_0: Component amm_conduit_fl_24b 1.0 not found or could not be instantiated

    Error: qsys-generate failed with exit code 3: 1 Error, 5 Warnings

    Besides this, the warning in the description indicates that there is no valid clocks found between the given points. You have to verify that there is a valid clock between the from and to collection.


    I can help you to check if you could provide the full design QAR. To generate QAR file, click on Project > Archive Project > Archive


    Thanks

    Best regards,

    KhaiY



    • JHaye4's avatar
      JHaye4
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Sorry for that, I have removed that specific IP from the QSYS as it is not related to the issue I'm having.

      I have attached my QAR as requested, thank you very much.