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JHaye4's avatar
JHaye4
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Constraints warning from async_clock_corsser

I am using a QSYS in my design and get the following warnings when compiling. I am instantiating a clock, constraining it correctly, and feeding it to the QSYS so I'm not sure what is going on. ...
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    5 years ago

    Hi James,


    I received the feedback from engineering. These warnings can be safely ignored. You may also use the sdc that I emailed to you to fix the warning.


    Thanks

    Best regards,

    KhaiY


KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Error below occurred during QSYS HDL generation.

Error: sys_f1_amm_conduit_fl_24b_0.amm_conduit_fl_24b_0: Component amm_conduit_fl_24b 1.0 not found or could not be instantiated

Error: qsys-generate failed with exit code 3: 1 Error, 5 Warnings

Error: sys_f1_amm_conduit_fl_24b_0.amm_conduit_fl_24b_0: Component amm_conduit_fl_24b 1.0 not found or could not be instantiated

Error: qsys-generate failed with exit code 3: 1 Error, 5 Warnings

Besides this, the warning in the description indicates that there is no valid clocks found between the given points. You have to verify that there is a valid clock between the from and to collection.


I can help you to check if you could provide the full design QAR. To generate QAR file, click on Project > Archive Project > Archive


Thanks

Best regards,

KhaiY



JHaye4's avatar
JHaye4
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Sorry for that, I have removed that specific IP from the QSYS as it is not related to the issue I'm having.

I have attached my QAR as requested, thank you very much.