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JHaye4's avatar
JHaye4
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Constraints warning from async_clock_corsser

I am using a QSYS in my design and get the following warnings when compiling. I am instantiating a clock, constraining it correctly, and feeding it to the QSYS so I'm not sure what is going on. ...
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    5 years ago

    Hi James,


    I received the feedback from engineering. These warnings can be safely ignored. You may also use the sdc that I emailed to you to fix the warning.


    Thanks

    Best regards,

    KhaiY


KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Which software edition (Pro/Standard) and version you are using? Could you share the design and steps to reproduce the error?


Thanks

Best regards,

KhaiY


JHaye4's avatar
JHaye4
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

I am using Quartus Pro 19.4. I have attached my qsys design that is in question.

I made sure to connect the inputs and outputs of the Qsys to pins in my top level module so that they are not synthesised away, all clock pins are being driven correctly. There is no real further logic in my top level module so I have not included it.