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Jack_H's avatar
Jack_H
Icon for New Contributor rankNew Contributor
11 months ago

Connecting SSGDMA to PCIe on Agilex 5e - Port Width Mismatch

Hi everyone,

I'm working on designing a PCIe device using the Agilex 5e chip and am trying to integrate DMA capabilities. Specifically, I'm using the Scalable Scatter-Gather DMA (SSGDMA) IP and connecting it to the GTS AXI Streaming Intel FPGA IP in Platform Designer.

However, I've run into an issue: the p0_st_cplto (complete timeout) master interface and the corresponding slave interface have different port widths. The PCIe IP's p0_ss_app_st_cplto_tdata has a width of 49 bits, whereas the SSGDMA's ss_app_st_cplto_tdata is only 30 bits wide.

Does anyone know how to resolve this port width mismatch? Alternatively, is there another recommended approach to add DMA functionality to a PCIe device in this setup?

Thanks in advance for any advice!

Pcie

3 Replies

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    11 months ago

    Hi Jack_H,


    Thanks for reaching out.


    In Agilex 5 devices, you need to connect SSGDMA IP to the GTS AXI Streaming Intel FPGA IP for PCIe for DMA functionality. This is the only approach available that I'm currently aware of.


    Please refer to the design example user guide to generate the design example. The warning of the difference in bit length of p0_ss_app_st_cplto_tdata can be safely ignored. Note that for the current QPDS Pro release v24.3, the SSGDMA IP Design Example in DMA PCIe mode is supported in compilation only.


    SSGDMA Design Example User Guide:

    https://www.intel.com/content/www/us/en/docs/programmable/823179/24-2-1-1-1/design-example-description.html


    Thanks.

    Best Regards,

    Ven


  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    11 months ago

    Hi Jack_H,


    May I know if you have further questions on this forum thread?


    Thanks.

    Best Regards,

    Ven


  • Jack_H's avatar
    Jack_H
    Icon for New Contributor rankNew Contributor
    10 months ago

    I see. Thanks. I have compiled the SSGDMA Design Example, and now I'm trying to access the Global CSR. I took a deeper look into the SSGDMA documentation, and found that the Global CSR through BAR0. I've tried to access these registers through the Ubuntu PCIe Driver that comes with the PCIe Design Example, but so far I couldn't make it work.

    Do you know how to access these registers via the driver?

    Best,

    Jack