Connecting SSGDMA to PCIe on Agilex 5e - Port Width Mismatch

Hi Jack_H,

Thanks for reaching out.

In Agilex 5 devices, you need to connect SSGDMA IP to the GTS AXI Streaming Intel FPGA IP for PCIe for DMA functionality. This is the only approach available that I'm currently aware of.

Please refer to the design example user guide to generate the design example. The warning of the difference in bit length of p0_ss_app_st_cplto_tdata can be safely ignored. Note that for the current QPDS Pro release v24.3, the SSGDMA IP Design Example in DMA PCIe mode is supported in compilation only.

SSGDMA Design Example User Guide:

https://www.intel.com/content/www/us/en/docs/programmable/823179/24-2-1-1-1/design-example-description.html

Thanks.

Best Regards,

Ven