Clocking Cyclone V Native PHY IP using Altera fractional PLL IP (LVDS Mode)

I'm trying to use the altera pll IP to clock (100mhz, lvds mode) the tx and rx cdr ref clock of the native phy IP. However, I'm receiving error messages during fitting saying that Quartus cannot find an available fpll location. This is for a board using Cyclone V SX C2 model without an external crystal oscillator driving the transceiver bank. I tried using the ALTCTRL IP to set the PLL clock as a global clock based on another message board post but it did not work.

Prior to this, I used this exact same Native Phy verilog code (xcvr, reconfig, reset) for an Intel C5 SX Dev Kit. I was able to clock the IP using the 100mhz hardware oscillator on that board and have the IP working correctly.

Is there something I'm missing, configuration or otherwise, when I switch from using a hardware crystal oscillator to using the alterall pll? I saw from previous posts that there used to be a Cyclone V fpll example for native phy IP, but I can't seem to find it anymore as the wiki links are broken.

Looking for advice and/or access to the example fpll native PHY IP. Thanks.