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Hamathon's avatar
Hamathon
Icon for New Contributor rankNew Contributor
2 years ago

Clocking Cyclone V Native PHY IP using Altera fractional PLL IP (LVDS Mode)

I'm trying to use the altera pll IP to clock (100mhz, lvds mode) the tx and rx cdr ref clock of the native phy IP. However, I'm receiving error messages during fitting saying that Quartus cannot find...
Transceiver
Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi,


As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you,

Kshitij Goel