Honored ContributorI have not successfully gotten Clocked Video Output to take dynamic configuration from it's slave port. I can use the wizard to configure it, but none of the 1-14 video modes will configure.
Yes, I set them invalid before changing the settings and then make them valid. However, according to the current mode register, it stays stuck at mode 0.
Honored ContributorOh Sorry. I assumed, you are using separate sync signals and not embedded with video.
Currently i don't have the development board to verify the clocked video output behavior. But may i ask, from where does this PAL video comes and what is the pixel clock and how is it generated. Just a suggestion, you can verify the altera avalon ST video control packets preceding the video frame and verify the resolution and format.Honored ContributorThe application is very-very simple. There is no external source. The source is a Test pattern Gemerator with approriate parameters (720x576, YCbCr, 4:2:2, 8 bit wide, sequence, interlaced). Just two componets are in the NIOS, this pattern generator, and the Clocked Video Output which has these parameters:
720x576, 8 bit, numof CP 2, sequence,, Interlaced, Emb. in video., PAL template is apllied, btw. Use control port is checked on, BUT I STILL DON'T HAVE ACCESS to the parameters in runtme.Honored ContributorI hope the number of runtime configurable modes in clocked video ip is set to atleast 3 or more than that.
and which is the clock to the clocked video output IP as pixel clock?Honored ContributorOf course 27MHz
Honored ContributorIf you mean to the inside clok that is 100 Mhz, the same as the CPU clk.
Honored Contributori meant, from where does this clock comes ?
Honored ContributorFor both clocks (inside for NIOS and for pixel clock) comes form external sources (50 Mhz osc) trough 2 pieces PLLs. Cyc3 dev kit board, btw...
The clock are very stable, with very-very small jitter. 1 have GHz scope with many channels... Thank you for youyr effort trying to help me!Honored Contributori am talking about the pixel clock to the clocked video IP.
I am not sure which board you are using to test this clocked video IP but it will go through the TV encoder chip before coming to the TV display. The decoder chip might have a output display modes. e.g the ch7010 on 3c120 board has few modes for PAL output and for 720x576 has 882x625 as actual resolution and thus clock will be 27.562500 MHz. and for proper pixel clock synchronization, you will need to run this TV encoder chip in master clock mode and use the output clock from this TV encoder chip as a pixel clock to the clocked video output IP. i am not sure about the values of registers in clocked video IP , as i never actually read back to check the value. and currently dont have development board to verify, as i mentioned earlier. But if its the pixel clock because of which, your output video looks broken (??) . then this might be the reason.Honored ContributorThis is not my first video project, I deal with such stuff now for 10 years, and also helped to well known chip maker companies in some chip development too, so I believe I know a lot about the encoder chips and the standards, resolutions.
But talking about the concrete problem... The encoder chip I use is my labor encoder and is used now for many years for different source testing, and of course it works with any other source. 882x625??? The active pixel resolution is 720x576 by the ITU BT or CCIR 601. Together with H blanking pixels is 864 (1728 bytes with TRS). V resolution is 625 (inc. VBI lines). 1728 x 625 x 25 (full frame == 50 interlaced) = 27 000 000, so that 27 Mhz.Honored ContributorOh i am not very experienced in the video projects. So i might not be very expert in giving solutions.
But have worked on the 3c120 development board and got the TV output working. And while working on this project, i came accross the problems which i found similar to your posting. So suggested the solutions, which i thought, you would find useful. anyways, i know for 720x576 active resolution, as per the standard, its 864x625 and thus 27 MHz. But i was telling about the TV output mode(mode 22) on CH7010d (Bitec Quad video board), which has 882x625 as actual resolution. but i think, you would be able to find solution for this particular board and problem better than me. all the best!
