Honored Contributor
Honored Contributori am talking about the pixel clock to the clocked video IP.
I am not sure which board you are using to test this clocked video IP but it will go through the TV encoder chip before coming to the TV display. The decoder chip might have a output display modes. e.g the ch7010 on 3c120 board has few modes for PAL output and for 720x576 has 882x625 as actual resolution and thus clock will be 27.562500 MHz. and for proper pixel clock synchronization, you will need to run this TV encoder chip in master clock mode and use the output clock from this TV encoder chip as a pixel clock to the clocked video output IP. i am not sure about the values of registers in clocked video IP , as i never actually read back to check the value. and currently dont have development board to verify, as i mentioned earlier. But if its the pixel clock because of which, your output video looks broken (??) . then this might be the reason.
