Occasional ContributorCan't simulate EMIF IP for Stratix 10 in ModelSim with generated design example?
I have the latest QuestaIntel Starter FPGA Edition-64 2023.2 and I'm trying to simulate a design example for a Stratix 10 by just clicking the simulation box in the EMIF IP to generate a test design example. I'm following the guide "External Memory Interfaces Intel Stratix 10 FPGA IP Design Example User Guide"
After generating the test design example, it gives me the directory that the file is saved under and folder name of emif_userdesign_example_design.
I startup Questa and go to change directory to the ModelSim directory that is saved under the test design example and type in source msim_setup.tcl and it generates a error message in red:
# could not read "../../ip/ed_sim/ed_sim_emif_s10_0/altera_emif_arch_nd_191/sim/ed_sim_emif_s10_0_altera_emif_arch_nd_191_ebuev6a_seq_params_sim.hex": no such file or directory
I can confirm the file does exist. It does not seem like it's able to read it though? How can I fix this to run the design example?
Problem is solved.
I had initially used the SystemBuilder, a third party app developed by Terasic to design and synthesize a design incorporating DDR4 memory. This was put on my desktop and design was under the Tools subfolder. I noticed that Questa was complaining that my design was not located in the Quartus Prime Pro directory under my C directory (the terminal indicated false false for c:\intelFPGA_pro\23.3\quartus). So I copied the entire design to this directory, then followed the directions in the Design Example Quick Start Guide for EMIF Stratix 10 FPGA IP to load the design in Questa and everything works fine. Was able to simulate the design.
