Forum Discussion
Occasional ContributorCan't simulate EMIF IP for Stratix 10 in ModelSim with generated design example?
Problem is solved.
I had initially used the SystemBuilder, a third party app developed by Terasic to design and synthesize a design incorporating DDR4 memory. This was put on my desktop and design was under the Tools subfolder. I noticed that Questa was complaining that my design was not located in the Quartus Prime Pro directory under my C directory (the terminal indicated false false for c:\intelFPGA_pro\23.3\quartus). So I copied the entire design to this directory, then followed the directions in the Design Example Quick Start Guide for EMIF Stratix 10 FPGA IP to load the design in Questa and everything works fine. Was able to simulate the design.
Occasional ContributorProblem is solved.
I had initially used the SystemBuilder, a third party app developed by Terasic to design and synthesize a design incorporating DDR4 memory. This was put on my desktop and design was under the Tools subfolder. I noticed that Questa was complaining that my design was not located in the Quartus Prime Pro directory under my C directory (the terminal indicated false false for c:\intelFPGA_pro\23.3\quartus). So I copied the entire design to this directory, then followed the directions in the Design Example Quick Start Guide for EMIF Stratix 10 FPGA IP to load the design in Questa and everything works fine. Was able to simulate the design.
