Forum Discussion
Occasional ContributorCan't simulate EMIF IP for Stratix 10 in ModelSim with generated design example?
Problem is solved.
I had initially used the SystemBuilder, a third party app developed by Terasic to design and synthesize a design incorporating DDR4 memory. This was put on my desktop and design was under the Tools subfolder. I noticed that Questa was complaining that my design was not located in the Quartus Prime Pro directory under my C directory (the terminal indicated false false for c:\intelFPGA_pro\23.3\quartus). So I copied the entire design to this directory, then followed the directions in the Design Example Quick Start Guide for EMIF Stratix 10 FPGA IP to load the design in Questa and everything works fine. Was able to simulate the design.
Occasional ContributorI'm using Quartus Prime Pro v. 23.3
and Questa Intel Starter Edition v. 2023.2 to stimulate.
Using Windows 11 OS.
I am using an updated version of the Document for EMIF, in specific the document updated for Quartus 21.1, IP Version 19.2.3.
According to the Document Revision history, there are no changes associated with simulating the IP, so they are the same.
That is correct, the "The default simulation directory will be at /emif_s10_0_example_design/sim/ed_sim/mentor"
I've also setup the change of directory information in Questa under File --> Change Directory.
This is the exact verbatin transcript of the simulation run when I input source msim_setup.tcl
Questa> source msim_setup.tcl
# [exec] file_copy
# could not read "../../ip/ed_sim/ed_sim_emif_s10_0/altera_emif_arch_nd_191/sim/ed_sim_emif_s10_0_altera_emif_arch_nd_191_elybpjy_seq_params_sim.hex": no such file or directory
I've attached the .tcl file for reference and zipped it because the forum won't allow the tcl file upload.
