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RHobb's avatar
RHobb
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Can't simulate EMIF IP for Stratix 10 in ModelSim with generated design example?

I have the latest QuestaIntel Starter FPGA Edition-64 2023.2 and I'm trying to simulate a design example for a Stratix 10 by just clicking the simulation box in the EMIF IP to generate a test design ...
Memory
  • RHobb's avatar
    RHobb
    2 years ago

    Problem is solved.

    I had initially used the SystemBuilder, a third party app developed by Terasic to design and synthesize a design incorporating DDR4 memory. This was put on my desktop and design was under the Tools subfolder. I noticed that Questa was complaining that my design was not located in the Quartus Prime Pro directory under my C directory (the terminal indicated false false for c:\intelFPGA_pro\23.3\quartus). So I copied the entire design to this directory, then followed the directions in the Design Example Quick Start Guide for EMIF Stratix 10 FPGA IP to load the design in Questa and everything works fine. Was able to simulate the design.

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hello Sir,


May I know which Quartus* version that you used?


Are you using Windows* or Linux* environment?


I assume you have followed the instruction in this link : https://www.intel.com/content/www/us/en/docs/programmable/683408/21-1-19-2-3/generating-the-emif-design-example-for.html


By default, the an example design will be generated as shown in Figure 4.

The default simulation directory will be at /emif_s10_0_example_design/sim/ed_sim/mentor


Is there any warning or error message while generating the example design?


Can you provide the msim_setup.tcl file in this forum?


Regards,

Adzim