Forum Discussion
Can't simulate EMIF IP for Stratix 10 in ModelSim with generated design example?
- 2 years ago
Problem is solved.
I had initially used the SystemBuilder, a third party app developed by Terasic to design and synthesize a design incorporating DDR4 memory. This was put on my desktop and design was under the Tools subfolder. I noticed that Questa was complaining that my design was not located in the Quartus Prime Pro directory under my C directory (the terminal indicated false false for c:\intelFPGA_pro\23.3\quartus). So I copied the entire design to this directory, then followed the directions in the Design Example Quick Start Guide for EMIF Stratix 10 FPGA IP to load the design in Questa and everything works fine. Was able to simulate the design.
Hello Sir,
Let's try to verify the file name.
The .hex file is generated with a random name such as ed_sim_emif_s10_0_altera_emif_arch_nd_191_qlmkdkq_seq_params_sim.hex.
Please verify the bold name is matching.
You can check in the QuestaSim too.
After you have changed the directory to mentor folder, it's will show "cd */mentor" command in the transcript.
Then you can run "cd ./../../ip/ed_sim/ed_sim_emif_s10_0/altera_emif_arch_nd_191/sim/" in the transcript.
Then you run "ls" to list the files inside that directory.
Then verify that the .hex file has similar name to the tcl script.
The tcl script that contains the file location is located in emif_s10_0_example_design/sim/ed_sim/common/modelsim_files.tcl
The file path may located around line 33 in modelsim_files.tcl.
For example at line 33, lappend memory_files "[normalize_path "$QSYS_SIMDIR/../ip/ed_sim/ed_sim_emif_s10_0/altera_emif_arch_nd_191/sim/ed_sim_emif_s10_0_altera_emif_arch_nd_191_qlmkdkq_seq_params_sim.hex"]"
Regards,
Adzim