Avalon_ mm_ master wrapper (vhdl)

Dear sir,

I have created the Custom component of CDMA_ENCODING and CDMA_DECODING as per Mr.Kevin Jennings suggestions.

NIOS-->(S)CDMA_ENCODING(M)-->(S)CDMA_DECODING-->slave

Now , while building my own system in SOPC builder.

i added components in this order.

NIOS

ONCHIP MEMORY

CDMA_ENCODING

CDMA_DECODING

SLAVE(SD RAM).

I am getting these errors:

cpu_0:nois ii instruction master cannot address memories over 2^32.

cpu_0:nois ii data master cannot address memories over 2^32.

memory map cannot fit within the addressable memory space of the nios ii data master which is restricted to 31 adress bits..

my both address and data masters are 32-bit only.

what is the cause of this error, and suggest me the possible solution .

thank you.

--- Quote Start ---

NIOS-->(S)CDMA_ENCODING(M)-->(S)CDMA_DECODING-->slave

Now , while building my own system in SOPC builder.

i added components in this order.

NIOS

ONCHIP MEMORY

CDMA_ENCODING

CDMA_DECODING

SLAVE(SD RAM).

I am getting these errors:

cpu_0:nois ii instruction master cannot address memories over 2^32.

cpu_0:nois ii data master cannot address memories over 2^32.

memory map cannot fit within the addressable memory space of the nios ii data master which is restricted to 31 adress bits..

my both address and data masters are 32-bit only.

what is the cause of this error, and suggest me the possible solution .

--- Quote End ---

- NIOS does not support 32 bit address space, only 31 bits. The slave interface needs to cut down by at least one bit...likely more since if you have a 31 bit slave device connected to the NIOS, then it will consume the entire address space, leaving no address space for anything else...such as memory to read the software program.

- Does the slave interface of 'CDMA_ENCODING' really have 2^32 addressable memory locations? That's an awful lot. How many registers/ports are really addressable? That will define how many bits wide the address bus needs to be.

Kevin Jennings

DEAR K_J,

oh my god, so much of patience you have to type this much...

thank you very much sir,i will be get back to you very soon... if i got any doubts again.

Dear K_J,

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First you'll need to decide whether the input and output interfaces of CDMA Encoding and Decoding should be 'pulled' or 'pushed' through the pipeline. This will determine if that interface is a 'master' or 'slave' interface in Avalon jargon.

An example of 'pushing' would be the encoding block simply outputs data when it has it available to send and it is expecting the receiver to catch it. In your example, you simply listed what looks to be the data path signals 'PI' and 'Output', but there are no signals to indicate when data is actually valid. An example of 'pulling' would be if the decoding block decided when it was ready to receive data from the upstream block which was then expected to supply the data.

To get a bit more concrete, you will have to look at each interfaces and decide based on your design which implementation is easiest to accomplish. The only hard and fast rule is that a 'master' talks only to a 'slave'; 'master' do not talk to each other, nor do 'slaves'. Every transfer is initiated by the 'master' and acted on by the 'slave'.

Here is your data flow

NIOS-->CDMA_ENCODING-->AVALON-->CDMA_DECODING-->SLAVE

And here I've pencilled in a possible implementation where (M) indicates the interface is a 'master', (S) indicates a 'slave'. Note that encoding and decoding blocks each have an input and an output interface.

NIOS-->(S)CDMA_ENCODING(M)-->(S)CDMA_DECODING(M)-->(S)SLAVE

or perhaps this, assuming that the output to what you called 'SLAVE' is not Avalon

NIOS-->(S)CDMA_ENCODING(M)-->(S)CDMA_DECODING-->SLAVE

Thanks in advance K_J.

Your other choice could be for the Avalon interface between the CDMA blocks could also be:

NIOS-->(S)CDMA_ENCODING(S)-->(M)CDMA_DECODING-->SLAVE

Again, whether you choose the connections between the two CDMA blocks is somewhat arbitrary, do what is convenient for you. The Avalon fabric will stitch together the 'master' to 'slave' logic, but you need to provide the 'master' and the 'slave'.

Once you have the flow control defined, then you look at the Avalon manual. Assuming you chose the following flow

NIOS-->(S)CDMA_ENCODING(M)-->(S)CDMA_DECODING-->SLAVE

Then then CDMA_ENCODING block is a master and is pushing data out to a slave. This means the following:

- CDMA_ENCODING needs to provide a 'write' and 'writedata' signals as outputs, and 'waitrequest' as an input.

- CDMA_DECODING needs to provide 'chipselect', 'write' and 'writedata' signals as inputs and (optionally) provide 'waitrequest' as an output.

If you refer to the Avalon manual it actually is pretty clear about what the signals definitions are, but you need to know what type of interface is needed and understand that each of the connections you show in your flow diagram represent interfaces.

It's actually not that hard once you get the first one or two under your belt and Avalon does provide a simple low overhead flow control mechanism that is almost always needed since there are very few cases where something can simply blast out data and expect something to be able to receive and process it on every clock cycle from here to eternity. Even if you were simply writing something to memory, a memory controller would always have to pause on occasion to generate a refresh to the memory device...which implies that something that is shoving data at it would have to pause as well which implies there has to be some signalling for data flow control.

Kevin Jennings

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--- Quote Start ---

NIOS-->(S)CDMA_ENCODING(S)-->(M)CDMA_DECODING-->slave

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if my case is above then what is the (M)CDMA_DECODING(?).. will it be slave port ? if its is a slave port is it possible to connect slave.

can i choose is both sides as master ports , so that i can connect to slave

--- Quote Start ---

- NIOS does not support 32 bit address space, only 31 bits. The slave interface needs to cut down by at least one bit...likely more since if you have a 31 bit slave device connected to the NIOS, then it will consume the entire address space, leaving no address space for anything else...such as memory to read the software program.

--- Quote Start ---

- Does the slave interface of 'CDMA_ENCODING' really have 2^32 addressable memory locations? That's an awful lot. How many registers/ports are really addressable? That will define how many bits wide the address bus needs to be.

--- Quote End ---

Kevin Jennings

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my custom logic does not store any thing,it does not have any registers . what ever the input it gets, it just encodes and gives out put. the ports are

before encoding:

address:8-bit

data:32 bit

after endoding

address : 4bit

data 16bit

after decoding

address:8bit

data:32bit

how to know that address range?

thanks.

--- Quote Start ---

if my case is above then what is the (M)CDMA_DECODING(?).. will it be slave port ? if its is a slave port is it possible to connect slave.

can i choose is both sides as master ports , so that i can connect to slave

--- Quote End ---

You didn't really indicate in any of your posts just what the 'SLAVE' device in your processing chain represents. I assumed it to be something external to Avalon that you just happened to call 'SLAVE'. If it is external to Avalon, then the output side interface of CDMA_DECODING with the (?) would not be an Avalon interface either...it would be whatever it is that 'SLAVE' is expecting to have as a controller.

Kevin Jennings

--- Quote Start ---

my custom logic does not store any thing,it does not have any registers . what ever the input it gets, it just encodes and gives out put. the ports are

before encoding:

address:8-bit

data:32 bit

after endoding

address : 4bit

data 16bit

after decoding

address:8bit

data:32bit

how to know that address range?

thanks.

--- Quote End ---

You've lost me. On the one hand you say that there are no registers but then you talk about 8 bit and 4 bit addresses. Which interface is generating the addresses (i.e. who is the Avalon master) and who is expected to receive them (i.e. who is the Avalon slave)? Can you map these to the blocks in the processing chain that you previously described and maybe sketch something out so it is clearer what interface has which addressing?

Kevin Jennings

Dear K_J,

I got the solution for address range problem.what ever is the slave address range(8 bit or 4 bit),master range must be atleast 32bit width.at this point master will use the byteenable signal,if not master will write spuriously into the slave.

now, can you tell me , how to use the byte enable signal in the master port,

any example code in vhdl.

Thank you K_J.

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now, can you tell me , how to use the byte enable signal in the master port,

any example code in vhdl.

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Refer to Table 3-1. Avalon-MM Signals in the Avalon specification for the exact definition. Basically though byte enable gets set by the master at the same point that it sets the address. So wherever it is that you have your logic that generates 'read' (or 'write') and 'address' you would need to also set 'byteenable'.

Below is an example template that shows how to properly generate all of master output signals. Not every master needs to both 'read' and 'write'; if not needed you simply can leave them off of the entity. You would need to fill in the ... with whatever your logic is for generating an address, when exactly a read or write should be initiated what data is to be written for a write and which bytes are to be selected.

If you only want to write to the lower 16 bits, byteenable would be set to "0011"; the upper 32 bits would be "1100"; writing only to the least significant byte would be "0001". In many cases though, you are always writing to all of the bytes so byteenable can simply be set to "1111" outside of the process since it is never changing. The value for byte enable is only needed during the time when a command is being issued, it is otherwise ignored. This is also true for address and writedata. That's why none of these signals needs to be reset by 'reset'. Some like to reset everything, I prefer not to burden a design with unnecessary logic since potentially it can become a performance or routing issue.

process(Clock)
begin
    if rising_edge(Clock) then
        if (Reset = '1') then
            read <= '0';    -- If this master reads
            write <= '0';   -- If this master writes
        elsif (waitrequest = '0') then  -- The signals can't change while waitrequest is active
            address <= .... -- However it is that the master is supposed to generate an address
            byteenable <= "1111";   -- Write to all 32 bits
            write <= ...    -- However it is that the master is supposed to initiate a write
            writedata <= ...-- Whatever it is that is supposed to be written
        end if;
    end if;
end process;

Kevin Jennings

Dear K_J,

Definitely i will include your name in my thesis K_J. Sure.

You are helping me a lot, really a lot.

Please send me a mail to [email protected].(just empty msg or about you).

i will get back to you soon, for further quires.

Thank you.