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Altera_Forum
Honored Contributor
14 years agoDear K_J,
I got the solution for address range problem.what ever is the slave address range(8 bit or 4 bit),master range must be atleast 32bit width.at this point master will use the byteenable signal,if not master will write spuriously into the slave. now, can you tell me , how to use the byte enable signal in the master port, any example code in vhdl. Thank you K_J.