Avalon_ mm_ master wrapper (vhdl)

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my custom logic does not store any thing,it does not have any registers . what ever the input it gets, it just encodes and gives out put. the ports are

before encoding:

address:8-bit

data:32 bit

after endoding

address : 4bit

data 16bit

after decoding

address:8bit

data:32bit

how to know that address range?

thanks.

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You've lost me. On the one hand you say that there are no registers but then you talk about 8 bit and 4 bit addresses. Which interface is generating the addresses (i.e. who is the Avalon master) and who is expected to receive them (i.e. who is the Avalon slave)? Can you map these to the blocks in the processing chain that you previously described and maybe sketch something out so it is clearer what interface has which addressing?

Kevin Jennings