Altera_Forum
Honored Contributor
Honored ContributorAvalon- Wishbone Wrapper OpenCores CAN Protocoll Controller
Hi, I know that this has been discussed in some old threats but I could not get some real help from those. I want to use the CAN Protocoll Controller in my NIOSII system designed with QSYS.
I took a look at the two bus specifications and came up with this wrapper:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity OC_Can is
port (
avs_s0_address : in std_logic_vector(7 downto 0) := (others => '0'); -- s0.address
avs_s0_read : in std_logic := '0'; -- .read
avs_s0_readdata : out std_logic_vector(31 downto 0); -- .readdata
avs_s0_write : in std_logic := '0'; -- .write
avs_s0_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avs_s0_readdatavalid : out std_logic; -- .readdatavalid
avs_s0_waitrequest : out std_logic := '0';
clk : in std_logic := '0'; -- clock.clk
reset : in std_logic := '0'; -- reset.reset
avs_irq_n : out std_logic; -- irq0.irq
clk_i : IN STD_LOGIC;
rx_i : IN STD_LOGIC;
tx_o : OUT STD_LOGIC;
bus_off_on : OUT STD_LOGIC;
irq_on : OUT STD_LOGIC;
clkout_o : OUT STD_LOGIC
);
end entity OC_Can;
architecture rtl of OC_Can is
COMPONENT can_top
GENERIC ( Tp : INTEGER := 1 );
PORT
(
wb_clk_i : IN STD_LOGIC;
wb_rst_i : IN STD_LOGIC;
wb_dat_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wb_dat_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
wb_cyc_i : IN STD_LOGIC;
wb_stb_i : IN STD_LOGIC;
wb_we_i : IN STD_LOGIC;
wb_adr_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wb_ack_o : OUT STD_LOGIC;
clk_i : IN STD_LOGIC;
rx_i : IN STD_LOGIC;
tx_o : OUT STD_LOGIC;
bus_off_on : OUT STD_LOGIC;
irq_on : OUT STD_LOGIC;
clkout_o : OUT STD_LOGIC
);
END COMPONENT;
signal wb_readdata : STD_LOGIC_VECTOR(7 downto 0);
signal wb_writedata : STD_LOGIC_VECTOR(7 downto 0);
signal wb_stb : STD_LOGIC;
signal wb_ack : STD_LOGIC;
signal wb_cyc : STD_LOGIC;
signal avs_irq : STD_LOGIC;
signal av_readdatavalid : STD_LOGIC;
begin
can_inst : can_top
PORT MAP
(
wb_clk_i => clk,
wb_rst_i => reset,
wb_dat_i => wb_writedata, --write data
wb_dat_o => wb_readdata, --read data
wb_cyc_i => wb_cyc, --when asserted indicates that valid bus cycle is in progress
wb_stb_i => wb_stb, --when asserted indicates that the slave is selected, slave should not respond till stb_i is asserted
wb_we_i => avs_s0_write, --deasserted during read cycles, asserted during write cycles
wb_adr_i => avs_s0_address,
wb_ack_o => wb_ack, --when asserted indicates termination of normal bus cycle
clk_i => clk_i,
rx_i => rx_i,
tx_o => tx_o,
bus_off_on => bus_off_on,
irq_on => avs_irq,
clkout_o => clkout_o
);
wb_stb <= avs_s0_read OR avs_s0_write;
wb_cyc <= avs_s0_read OR avs_s0_write;
avs_s0_waitrequest <= not wb_ack;
avs_s0_readdatavalid <= wb_ack;
--extend 8bits coming from can core to full 32 bits for avalon
avs_s0_readdata <= "000000000000000000000000" & wb_readdata;
--map lowest 8bits coming from avalon to writedata of can core
wb_writedata <= avs_s0_writedata(7 downto 0);
--avs_s0_readdatavalid <= '0';
avs_irq_n <= not avs_irq;;
end architecture rtl; -- of OC_Can
# include <stdio.h># include <io.h># include "system.h"# include "sys/alt_stdio.h"
int main()
{
unsigned int temp;
printf("Hello from Nios II!\n");
temp = IORD_32DIRECT(OC_CAN_0_BASE,4);
printf("%u",temp);
while(1);
return 0;
}
